The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 1986

Filed:

Aug. 04, 1983
Applicant:
Inventor:

Nico F Benschop, Eindhoven, NL;

Assignee:

U.S. Philips Corporation, New York, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307481 ; 307450 ; 307453 ; 377 79 ; 377105 ;
Abstract

A MOS integrated logic circuit is described which comprises a plurality of groups (61, 63, 65, 67, 69) of combinatory logic elements. These groups form a cascade in that a data output of a preceding group is directly coupled to a data input of a next group within the cascade. During successive clock pulse phases the groups of combinatory logic elements are sampled in the sequence in which they are arranged in the cascade. Charging means provide the charge to be sampled, either by means of a precharge clock phase, or by virtue of being pull-up means.


Find Patent Forward Citations

Benschop, Nico. (1986). Integrated logic circuit incorporating fast sample control (U.S. Patent No. 4567386). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4567386

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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