The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 1986

Filed:

Aug. 05, 1983
Applicant:
Inventor:

David L Campbell, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B / ;
U.S. Cl.
CPC ...
331 57 ; 331 34 ; 3311 / ; 331143 ; 307455 ;
Abstract

The fall-time of an ECL gate is precisely controlled using a fixed capacitor, which is connected between the positive supply voltage and the ECL gate output terminal, and a variable current source connected between ground and the ECL gate output terminal. A time-delay circuit is obtained by controlling the variable current source with an error voltage of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates with controlled fall-times in a ring oscillator configuration. Addition of a non-inverting input to one ECL gate makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided by phase-locking the output signal of a first phase-locked loop to a system reference signal to generate a first-loop control voltage. A second phase-locked loop is phase-locked to the received signal with a second-loop control voltage. In addition, the second phase-locked loop is also frequency-locked to the system reference signal by the first-loop control voltage. This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal.


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