Semiconductor memory

Abstract

A semiconductor memory has dynamic memory cells, such as one-MOS transistor cells, a detector circuit which detects changes in applied address signals, and a timing generator circuit which receives detection outputs of the detector circuit. When the address signals are changed, various timing signals are responsively produced from the timing generator circuit. In response to the timing signals generated in succession, data lines to which the memory cells are coupled are first precharged, and one of the memory cells is selected after the precharge of the data lines. Data delivered from the selected memory cell to the data line is amplified when the operation of a sense amplifier is started. The amplified data is supplied to an external terminal through a column switch, a main amplifier, an output amplifier, etc., which are similarly operated in succession. Since the semiconductor memory of this arrangement forms a pseudo-static memory, it requires only a small number of external timing signals. In order to obtain a desirable pseudo-static memory, a data line precharge level is equalized to half of the supply voltage level, and the sense amplifier is constructed of a CMOS-FET latch circuit. As a result, the period of time from the change of the address signals until the delivery of the output data can be sufficiently shortened. It is therefore possible to form a pseudo-static memory which is, in effect, regarded as a static memory.