The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 1986

Filed:

Jun. 01, 1983
Applicant:
Inventor:

Kazuo Suganuma, Yokohama, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F / ;
U.S. Cl.
CPC ...
364784 ; 307472 ;
Abstract

A full adder is disclosed which comprises a first exclusive OR circuit for OR processing a first input signal and a second input signal, a second exclusive OR gate for OR processing an output signal of the first exclusive OR gate and a third input signal, and select circuit for selecting one of the first and second input signals and the third input signal according to a logical level of the output signal of the first exclusive OR gate. A sum signal of the first to third input signals, is obtained by the first exclusive OR means and the second exclusive OR means. The select means selects either the first or second input signal or the output signal of the third input signal according to a logical level of the output signal of the first exclusive OR means. The selected signal is used as a carry signal.


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