The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 1985

Filed:

Jan. 23, 1984
Applicant:
Inventors:

Hiroyuki Kudo, Hitachi, JP;

Atsumi Watanabe, Hitachi, JP;

Hiroshi Sasaki, Hitachi, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H / ;
U.S. Cl.
CPC ...
361 85 ; 361 82 ; 361 84 ; 361 67 ;
Abstract

A protective relay which hardly makes maloperation in itself regardless of mixing of low-order higher harmonics in its at least two sinusoidal input signals comprises a first and a second phase detection comparator generating two different-phase square signals indicative of the phase difference between the sinusoidal input signals, a first and a second timer receiving the square signals generated from the first and second phase detection comparators respectively and generating their output signals as a result of comparison between a first period of time and one of the periods or the period of presence or absence of the square signals, a third timer receiving the same square signal as that applied to the first timer and generating its output signal as a result of comparison between a second period of time and the other period or the period of absence or presence of the square signal, a fourth timer receiving the same square signal as that applied to the second timer and generating its output signal as a result of comparison between the second period of time and the other period or the period of absence or presence of the square signal, a first flip-flop set by the first timer and reset by the third timer, a second flip-flop set by the second timer and reset by the fourth timer, and a third flip-flop set and reset by an AND circuit and a NOR circuit respectively connected to the outputs of the first and second flip-flop.


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