The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 1985
Filed:
Aug. 31, 1983
William A White, Garland, TX (US);
Mooshi R Namordi, Acton, MA (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A MESFET logic gate wherein a logic switch node is both a-c coupled to the output node, preferably by a capacitor network and is also separately DC coupled to it, preferably by a voltage level shifter circuit. The direct capacitative coupling increases the high-frequency cut-off frequency, and reduces the current requirement of the voltage level shifter circuit. The voltage level shifter circuit, even using small width devices, provides low frequency and DC response, so that circuits using the gate of the present invention do not require initialization and refresh cycle. Thus, both high speed and low power are attained.