The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 1985

Filed:

Mar. 23, 1984
Applicant:
Inventor:

Tatsuo Tanaka, Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03G / ;
U.S. Cl.
CPC ...
320-1 ; 307109 ;
Abstract

A charging/discharging circuit is formed of transistors Q1, Q2; resistors R1-R4; and a capacitor C. The series resistors R1, R2 are connected between the power supply line +Vcc and the circuit ground. The series resistors R3, R4 are connected between the line +Vcc and the circuit ground. The collector of NPN transistor Q1 is connected to +Vcc, the base thereof is connected to the junction between R3 and R4, and the emitter thereof is coupled to the junction between R1 and R2. The collector of PNP transistor Q1 is connected to the circuit ground, the base thereof is connected to the junction between R3 and R4, and the emitter thereof is coupled to the junction between R1 and R2. Capacitor C is connected in parallel to R2. The charged voltage of C is used as a reference potential VR for another linear circuit. Suppose that R1=R2, R3=R4 and +Vcc=10 V. When +Vcc rises from 0 V to 10 V but VR does not reach to 5 V, Q1 is forwardly biased so that C is quickly charged by the emitter current of Q1. When +Vcc falls from 10 V to 0 V but VR does not reach 0 V, Q2 is forwardly biased so that C is quickly discharged by the emitter current of Q2. When VR=5 V (stationary state), Q1 and Q2 are both cut-off, so that only small currents flow through the series circuits of R1, R2 and R3, R4. The time constant of (R1.vertline..vertline.R2).C can be made large so that VR is free from ripples of +Vcc.


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Tanaka, Tatsuo. (1985). Charging/discharging circuit (U.S. Patent No. 4555655). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4555655

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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