Memory utilization control system for compressed digital picture data

Abstract

An improved memory utilization control system for compressed digital picture data transmission systems, comprises an input terminal coupled to the memory circuit having a capacity of one frame, an address signal generator generating an address signal which successively indicates write-in addresses in first and second memory regions each amounting to one field in the memory circuit when picture element data of frame-transmission to be reproduced in the first and second fields are applied to the input terminal, and for generating two address signals which respectively and successively indicate write-in addresses in the first and second memory regions when picture element data of field-transmission are applied to the input terminal, a write-in pulse generator generating write-in pulses for writing the picture element data into the memory circuit, and a read-out control circuit for reading out stored picture element data from the first memory region during reproduction of the first field, and for reading out stored picture element data from the second memory region during reproduction of the second field, so that a total capacity of the memory circuit required otherwise is reduced drastically.