The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 1985
Filed:
Jun. 09, 1983
Applicant:
Inventors:
Hirofumi Takeda, Yokohama, JP;
Hirokazu Suzuki, Yamato, JP;
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307455 ; 307443 ; 307355 ; 307475 ; 307608 ; 3072 / ;
Abstract
An emitter coupled logic circuit includes a differential transistor pair and a set transistor, which are all emitter coupled. The logic level of the high voltage side of a set input signal to be applied, as a control input signal, to the set transistor is higher than the logic level of the high voltage side of the logic input signal pair to be applied, as control input signals, to the differential transistor pair. Simultaneously, the logic level of the low voltage side of the set input signal is lower than the logic level of the low voltage side of the logic input signal pair.