The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 1985

Filed:

Sep. 08, 1983
Applicant:
Inventors:

Kouichi Nagasawa, Kunitachi, JP;

Shuji Ikeda, Koganei, JP;

Norio Suzuki, Kodaira, JP;

Yoshio Sakai, Hachiouji, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
29571 ; 2957 / ; 148-15 ; 148187 ; 357 42 ; 357 91 ;
Abstract

Disclosed is a method of manufacturing a semiconductor device which includes MOSFETs of the two-channel conductivity types of P- and N-channel types on a single semiconductor substrate. According to the present invention, a first mask and a second mask are used. The first mask covers that surface part of the semiconductor substrate in which the P-channel type MOSFET is to be formed, and it serves as a mask when an N-type impurity is introduced into the semiconductor substrate. The first mask has a property and etching rate different from those of a film formed by the thermal oxidation of the semiconductor substrate surface. The second mask covers that surface part of the semiconductor substrate which has been formed with the N-channel type MOSFET, and it serves as a mask when a P-type impurity is introduced into the semiconductor substrate. The second mask is used as an inter-layer insulator film.


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