Apparatus for creating a multiplication pipeline of arbitrary size

Abstract

A multiply pipeline with parity circuit to be used as a building block in a multiplication pipeline of arbitrary size is disclosed. It includes circuits for generating and checking parity. The parity of the output carries leaving the component chips of the multiply pipeline are explicitly generated internally to those chips. By generating output carry parity on-chip, all single-bit errors except for those caused by on-chip internal gate or metallization faults will be detected. Thus, means are provided for detection of single-bit errors in the multiplication circuitry. The proposed multiply pipeline with parity circuit includes a pair of gate arrays, or chips, which participate as follows. A 6-bit by 6-bit multiply with parity chip is used as a building block in a portion of the pipeline in which all logical products are initially generated, and reduction of these logical products, or partial products, commences. A 6-bit by 4-bit adder/register with parity chip is used as a building block in subsequent sections of the pipeline, which are used to further reduce the partial products. This latter chip type also contains a latch register to provide orderly and controlled staging of the intermediate partial products.