The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 1985
Filed:
Jun. 20, 1983
Randall M Chung, Laguna Niguel, CA (US);
Larry D Rossean, Westminster, CA (US);
Western Digital Corporation, Irvine, CA (US);
Abstract
An improved chip topography for a disk memory controller circuit is provided which includes electrical interface circuitry disposed around the periphery of the chip and forming an approximately quadrilateral framework surrounding the remainder of the circuitry, a read-only-memory (ROM) disposed in one corner of the interface framework; a microcontroller disposed adjacent to the ROM and along part of a first side of the interface framework; read data processing circuitry disposed adjacent to the microcontroller and within a second corner of the interface framework and along part of a second side thereof; error checking circuitry disposed adjacent to the read data processing circuitry and along part of the second side of the interface framework; the microcontroller also being disposed adjacent to the error checking circuitry and along part of the second side of the interface framework; write data processing circuitry disposed adjacent to the microcontroller along the second side of the interface boundary, within a third corner of the interface framework and along a part of a third side of the interface boundary; the microcontroller also being disposed adjacent to the write data processing circuitry and along the third side of the interface framework; input/output (I/O) buffer/latch circuitry disposed adjacent to the micro controller along the third side of the interface framework, which is also disposed within the fourth corner and along a part of a fourth side of the interface framework, the microcontroller also being disposed adjacent to and between the I/O buffer/latch circuitry and the ROM along the fourth side of the interface framework; and task registers disposed between the microcontroller and the I/O buffer/latch circuitry.