Field effect transistor device utilizing critical buried channel

Abstract

The invention provides a new structure for a subsurface junction field effect transistor (SJFET) and a new process for its fabrication, the process being especially compatible with existing processes for the fabrication of bipolar devices. Spaced zones of p.sup.+ type are diffused into an n-type epitaxial layer to terminate the channel and connect to source and drain terminals. Spaced zones of n.sup.+ type are diffused into the epitaxial layer to define the channel width. The corresponding zones for the bipolar device can be formed at the same time. A passivating layer of silicon dioxide is applied and the subsurface p-type channel formed by ion implantation to leave a thin n-type layer between the channel and the silicon dioxide layer. Upon application of a metal layer over the silicon dioxide layer in the neighborhood of the channel, and its connection to the back gate terminal, a stable electron accumulation layer forms at the surface of the n-type layer which interfaces with the silicon dioxide layer. This electron accumulating layer buffers the device against variations in the characteristics of the silicon dioxide layer and its interfaces with the adjacent layers. The resultant matching of devices on the same chip or wafer is equivalent to that of more complex and time-consuming prior art processes requiring a second implant step to produce a buffering n.sup.+ type layer.