The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 1985
Filed:
Mar. 30, 1984
Terence G Cole, Southampton, GB;
Roderick M West, Southampton, GB;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A step waveform generator includes a cup and bucket circuit in which charging and discharging a cup capacitor (C1) with predetermined units of charge is achieved, in response to a train of pulses supplied to its input terminal (1), by means of an operational amplifier (2) continuously monitoring the voltage across the cup capacitor and alternately supplying charging current and discharging current from a first and second constant current source (I1 and I2) respectively via separate feedback loops (T3, T2 and T4, T7, T6) of the amplifier. The constant currents, or multiples or sub-multiples of the constant currents, providing each individual unit of charge, are generated by current mirrors (T8, T9, T10) and added sequentially to a bucket capacitor C2. The size of each individual step of the resultant voltage waveform derived from the bucket capacitor and appearing at output terminal 4 depends upon the combination of mirrored increments of current selected by switch (S1, S2) and added to the bucket capacitor. The waveform generator is particularly useful when driven by CRT horizontal sync pulses to provide a vertical timebase circuit generating a stepped voltage waveform instead of the more customary ramp voltage waveform. Appropriate combination of the outputs of the mirrors by judicious operation of the switches S1, S2 controls field interlace and single and multiple line skips.