Debounce circuit providing synchronously clocked digital signals

Abstract

An improved debouncer circuit is disclosed for providing debounced, synchronously clocked digital signals from a single-throw switch, as for instance, of the momentary contact type. A signal, variable between two logic levels, is provided by the switch for input to the debouncer circuitry. That input signal is applied as one input to an EXCLUSIVE OR gate, the other input to that gate being fed back from the Q output terminal of an output data latch having complementary Q and Q* output terminals. A signal representing the Q* output terminal of the data latch is connected to the D input of that latch such that a synchronous latch clocking signal appearing at the clock input of the output data latch serves to toggle the states of the Q and Q* output terminals. The signal appearing at either one of the output terminals Q, Q* of the output data latch may be used as the debounced signal provided to other circuitry, depending upon signal polarity needs. The clocking signal which toggles the output data latch is the output of a NAND gate. The inputs to the NAND gate include one phase of a two-phase synchronous clock signal, the output of the EXCLUSIVE OR gate, and the signal from the Q output of a second data latch. The second data latch is clocked by the other phase of the two-phase synchronous clock. The D input of the second data latch is connected to the output of an AND gate, with the inputs to the AND gate being provided by the O* output of the second data latch and by the output of the EXCLUSIVE OR gate.