Dot image buffer and dot sequence scrambler for dot matrix line printer

Abstract

In a dot matrix printer, a single main shift register is loaded in the non-printing time during which a transversely shuttling print bar is changing direction with the complete dot row to be printed on the next printing pass of the print bar. A custom VLSI integrated circuit comprising a serial loaded 2772-bit main shift register and a parallel loaded 132-bit bidirectional parallel-to-serial output shift register is provided. The main shift register has one storage cell for each dot that can be printed across the dot row during a single pass of the print bar. Parallel output taps physically placed along the main shift register provide simultaneous serial output of the storage cells between each tap. The number of bits stored between each output tap is the number of dots each individual print hammer can print on a single pass of the print bar. The 132-bit output shift register is utilized to limit the number of package pins and to compensate for the direction of motion of the print bar. The parallel outputs of the main shift register comprise the parallel inputs of the output shift register. Dot Generation Logic is provided to map printable characters and data through dot image character sets and to load the 2772-bit main shift register with the exact dot image of the data to be printed during the next pass of the print bar.