Phase locked loop for high speed data

Abstract

A phase locked loop circuitry for high frequency digital electronic signals is provided which includes a loop filter having a substantially infinite bandwidth and wherein the sum of the frquency comparator and phase comparator output signals is actively integrated by an operational amplifier and summed with a flat, passively attenuated signal from the phase comparator. The PLL circuit includes a phase comparator having a full adder employing current mode logic so as to reduce parasitic capacitances and stray voltages, a frequency comparator having an additional, final flip-flop means out of the final combinatorial logic so as to retain the polarity of the final waveform transition, and an inhibiting circuit to disable the output of the final flip-flop of the frequency comparator when phase lock is attained by adding a complementary signal thereto.