The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 1985
Filed:
Jun. 05, 1980
William H Ambrosius, III, Mission Viejo, CA (US);
Larry D Rossean, Santa Ana, CA (US);
Western Digital Corporation, Newport Beach, CA (US);
Abstract
An optimum chip topography for a MOS LSI Data Encryption Standard (DES) circuit, including interface and input/output circuitry disposed around the periphery of the chip, control circuitry disposed in a substantially rectangular area across the upper one-third of the surface of the chip, and, disposed on approximately the lower two-thirds of the surface of the chip and perpendicular to the control circuitry area, and arranged from one side of the chip to the other side of the chip, a key register, permuted choice circuitry, a first combinatorial circuit, a right data register, a second combinatorial circuit, a left data register, a P-combinatorial circuit, a first programmable logic arry group, and a second programmable logic array group. The bonding pad sequence for the MOS DES circuit chip is selected to allow the chip to be placed in either a 40-pin dual-in-line package or a 28-pin dual-in-line package. The bonding pad sequence for the MOS DES circuit chip is also selected to allow optimum arrangement of packages containing the DES circuit chips on a printed circuit board. Repetitive circuit cells and custom drawn circuit cells are both utilized so as to optimize use of semiconductor chip area.