Amenable logic gate and method of testing

Abstract

A multiple input logic gate that is amenable to full testability without the 'buried logic' problem of conventional VLSI logic devices and a novel dynamic test method for increasing fault-free production and simplified analysis of sub-chip faults. In one disclosed illustrative embodiment of the logic gate of the invention, the device comprises a replicated, hierarchial arranged group of six two-variable input gates to form a three-variable input gate and two such three input gates and associated logic control structure are provided on a single VLSI integrated circuit chip. Each two-variable input gate is controlled by its own programmed logic array thereby providing a selection of any of the possible 256 Boolean functions for each of the three-variable input gates on a chip. A highly advantageous dynamic test method exploits the regular hierarchial architecture of the inventive logic gate to provide top-down evaluation of each two-variable input gate until the six-gate structure is fully tested. The test method is implemented by clocking the two-variable input gates through their respective sixteen Boolean function sequentially and displaying a video map of gate output signals which will conform to a specified pattern when the device is fault-free.