The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 1985
Filed:
Aug. 03, 1982
Applicant:
Inventor:
Motonobu Nagafuji, Hadano, JP;
Assignee:
Hitachi, Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364749 ;
Abstract
An arithmetic logic unit processes a variable operand length instruction such as a decimal arithmetic operation instruction, a plurality of bytes at a time using a multi-byte depth arithmetic operation unit. Multi-byte data including first and second operands are supplied to the arithmetic logic unit through a suppressing circuit. The suppressing circuit suppresses unnecessary bytes other than operand bytes and suppresses all of the bytes of one of the operands when the one operand has been exhausted.
Nagafuji, Motonobu. (1985). Arithmetic logic unit (U.S. Patent No. 4542476). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4542476
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