The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 1985
Filed:
Jun. 15, 1984
James R Butler, San Jose, CA (US);
Precision Monolithics, Inc., Santa Clara, CA (US);
Abstract
A JFET differential amplifier stage in which the gate-drain voltage of each JFET is kept at least as great as the pinchoff voltage (V.sub.p), but preferably close to V.sub.p so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias currents. The JFETs are supplied with currents which force their gate-source voltages to at least 0.5 V.sub.p. A second pair of JFETs are cascoded with the first pair and also develop gate-source voltages of at least 0.5 V.sub.p. The gate-source terminals of the second pair are connected in a loop with the source-drain terminals of the first pair, thereby forcing the gate-drain voltages of the first pair to at least V.sub.p, the minimum voltage necessary to hold the first pair in a desired saturated state. A third pair of JFETs is connected to buffer the first pair from capacitances developed at the gates of the second pair without effecting the AC operation of the circuit.