The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 1985

Filed:

Sep. 14, 1983
Applicant:
Inventors:

Keiichi Sakurai, Tokyo, JP;

Hideaki Ishida, Tokyo, JP;

Kohtaro Hanzawa, Tokyo, JP;

Assignee:

Casio Computer Co., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G10H / ;
U.S. Cl.
CPC ...
84-126 ; 84-113 ;
Abstract

Under the presence of an internally generated mandolin clock (MDN) or an externally generated mandolin clock (MDN'), an envelope clock (ENV-CLK) obtained in accordance with a lower bit output having three-bit signals (including the LSB) is supplied through AND gates to an envelope counter. The counter is set in an up count state in response to an output from a flip-flop set in response to a key on pulse. When a carry signal is generated by the envelope counter, the counter is set in a down count state. In the latter case, the fourth-bit signal from the LSB of the output from the binary counter is gated through the AND gate. The envelope counter counts down the envelope clock (ENV-CLK) having a period twice that of the envelope clock (ENV-CLK) in the up count state.


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