The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 1985
Filed:
May. 11, 1984
Yoshihisa Takayama, Kawasaki, JP;
Kunihiko Gotoh, Kunitachi, JP;
Akihiko Ito, Kawasaki, JP;
Takeshi Yamamura, Zama, JP;
Kazuyoshi Fujita, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A programmable integrated circuit has multi-layer wiring with openings over fuses, and a fabrication method forms the openings for each fuse, to avoid damage due to the blowing off of the fuses. The forming of the openings is performed by etching each insulating layer on the fuses after it is formed over the pre-formed wiring-layers. This results in shorter etching time as compared to the prior art etching method where the openings are etched in all the layers for the whole depth in one process step. Because of the shorter time necessary for each etching, overetching and side-etching are reduced, thus providing the openings with more accurately determined dimensions, which provides higher yield for manufacturing the device. The contact holes and the windows for the bonding pads in each insulating layer are etched in the same fabrication step for forming the openings for the fuses in the same insulating layer. This requires no additional fabrication processes for the IC and results in no increase of the fabrication time and cost.