The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 1985

Filed:

Jun. 03, 1982
Applicant:
Inventor:

Lee R Reid, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365 63 ; 365 51 ;
Abstract

A memory circuit including several semiconductor substrates, each containing addressable memory elements, address receiving circuitry for receiving address signals and for providing data from the memory in response to the address signals, control circuitry for receiving control signals and for controlling the reading and writing of the memory elements, and interconnection circuitry including elevated portions of the semiconductor substrate connected to contact paths of the semiconductor substrate located above to provide electrical continuity between the addressable circuits of each semiconductor substrate and electrical continuity between the control circuits of each semiconductor substrate.


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Reid, Lee. (1985). Solid state three dimensional semiconductor memory array (U.S. Patent No. 4535424). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4535424

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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