The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 1985

Filed:

Jul. 08, 1982
Applicant:
Inventors:

Takaaki Yamada, Zama, JP;

Takeo Sekino, Atsugi, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
3403 / ; 307361 ;
Abstract

An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits includes at least (2.sup.m+n -1) resistors connected in a series circuit to a voltage source for establishing respective reference voltages; at least (2.sup.m -1) upper bit voltage comparators for generating outputs indictive of the m upper bits, and having first and second inputs, the analog input voltage being applied to the first inputs and the second inputs being connected to the series circuit at respective intervals defining groups of the resistors; an upper bit encoder receiving the outputs of the upper bit voltage comparators and generating a switch control signal and a digital output voltage signal of m upper bits; at least (2.sup.n -1) lower bit voltage comparators for generating outputs indicative of the n lower bits, and having first and second inputs, the analog input voltage signal being applied also to the first inputs of the lower bit voltage comparators; switch elements associated with each of the groups and being responsive to the switch control signal for selectively connecting the second inputs of the lower bit comparators to respective resistors in the associated resistor groups; and a lower bit encoder receiving the outputs of the lower bit voltage comparators and generating a digital output voltage signal of n lower bits.


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