The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 1985

Filed:

May. 13, 1983
Applicant:
Inventor:

Tadashi Noguchi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F / ;
U.S. Cl.
CPC ...
330307 ; 330254 ; 455194 ;
Abstract

A circuit for preventing malfunction of a muting amplifier is provided. The circuit of a muting amplifier is composed a semiconductor integrated circuit which comprises a first lateral p-n-p transistor to receive an input signal applied to the base thereof and one or more second lateral p-n-p transistors serving as a constant current source and performs an amplifying operation during the conduction of the second lateral p-n-p transistors or is placed in a muting mode during the cutoff thereof, the circuit configuration of this invention is such that a third p-n-p transistor is provided in the vicinity of the first lateral p-n-p transistor and is so connected as to turn on the second lateral p-n-p transistors during the conduction of the third p-n-p transistor, wherein, when the input signal level becomes lower than the minimum potential in the integrated circuit, the third transistor is turned on by an n-p-n transistor, which works as a parasitic transistor. Applying the current introduced by another parasitic p-n-p transistor in the direction reverse to the current caused by the foresaid parasitic n-p-n transistor can eliminate the disadvantage in the conventional circuit configuration.


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