The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 1985

Filed:

Dec. 09, 1982
Applicant:
Inventor:

William R Livesay, San Diego, CA (US);

Assignee:

Electron Beam Corporation, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01J / ;
U.S. Cl.
CPC ...
2504911 ; 2504922 ;
Abstract

Apparatus and a corresponding method for the alignment of an electron image projected from a patterned subfield of a cathode mask, with a corresponding subfield area of a semiconductor wafer to be exposed with the image. The apparatus includes a metalic detector positioned in a parallel relationship with the wafer and electrically biased to minimize distortion of an electric field used to accelerate electrons from the mask to the wafer, and a set of alignment marks disposed about the periphery of the wafer subfield area. A projected image of corresponding alignment marks on the mask passes through an opening in the detector layer, impinges on the wafer alignments marks, and causes some electrons to be back-scattered back through the opening and onto the detector layer. Use of the alignment technique results in significantly improved overlay precision, without wastage of useful wafer area and without significant distortion of the projected images. A disclosed embodiment of the invention employs a detector layer having multiple openings, positioned over multiple wafer subfield areas, which are successively aligned with and exposed to corresponding subfields of the mask, the detector layer being then moved laterally before the alignment and exposure of additional multiple subfield areas of the wafer.


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