Short-circuit-protected evaluation circuit of high stability for

Abstract

The inductance of a variable inductor is put in series with a resistor to provide a delay circuit at the output of an amplifying path and the delayed voltage is fed-back to produce square waves having a period representative of the induct. The amplifying path includes a first amplifier and a final stage that includes a transistor. A second transistor is connected to a voltage supply line feeding the final stage and the delay network and is also connected to the final stage in such a way that the second transistor conducts when the first transistor of the final stage is blocked and so that the second transistor is automatically blocked when the output of the final stage is at a low potential. The base of the second transistor is connected through a resistance to a battery voltage line at a somewhat higher potential than that of the voltage supply line for the final stage. It is useful to provide an additional amplifier to operate the second transistor with its input coming from the feed back line supplied by the variable inductor and its network resistor, preferably through a low-pass filter. For adjustments that may be necessary when the inductor of a system is replaced, the characteristic curve of the evaluation circuit can be additively shifted by interposing a resistance-capacitance delay followed by an amplifying comparator in the amplifying path, preferably between the preliminary amplifier and the final stage.