The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 1985
Filed:
Mar. 14, 1984
Erwin P Jacobs, Vaterstetten, DE;
Ulrich Schwabe, Munich, DE;
Siemens Aktiengesellschaft, Berlin & Munich, DE;
Abstract
A method for manufacturing a CMOS circuit wherein a process sequence matched to an n-tub manufacture is carried out. Short-channel properties of n-channel transistors are improved by performing double boron implantations of the channel regions. A single channel implantation is executed for both transistor types. Compared to traditional CMOS processes in n-tub structure, this eliminates involved masking steps. Also, the polysilicon gate is shielded from the boron ion implantation by means of a masking re-oxidation step and the under-diffusion given n-channel and p-channel transistors is greatly reduced by means of pull-back of the boron source/drain implantation. This contributes significantly to a symmetrical U.sub.T behavior of the transistors and to the attainment of high switching speeds. The method is used in the manufacture of VLSI CMOS circuits in VLSI technology.