The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 1985

Filed:

Aug. 11, 1982
Applicant:
Inventors:

Atsushi Iwata, Tokorozawa, JP;

Takao Kaneko, Tokorozawa, JP;

Akihiko Ito, Kawasaki, JP;

Tadahiro Saito, Kawasaki, JP;

Hirokazu Fukui, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L / ;
U.S. Cl.
CPC ...
331 17 ; 331-8 ; 331 25 ; 328155 ;
Abstract

A phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter. The signals corresponding to the output signals produced by the voltage-controlled oscillator are supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal. In the present invention, the loop filter comprises a first capacitor connected to the output terminal of the loop filter, second and third capacitors, each having a terminal connected to the output terminal of the loop filter, and a charging circuit for electrically charging the first, second, and third capacitors. The charging circuit is connected in parallel with the second capacitor. A discharging circuit for discharging the first, second, and third capacitors is connected in parallel with the third capacitor.


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