Read error occurrence detector for error checking and correcting system

Abstract

An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding system for generating a plurality of check bits, each check bit associated with a predetermined bit grouping of data bits within a data word. When a data word is accessed, read check bits are reconstituted from the read data and are compared to the check bits originally encoded. Syndrome bits are generated from the originally encoded check bits and the reconstituted read check bits, the syndrome bits thus generated, serving to identify whether the data word accessed contains no errors, a single bit error, or a multiple bit error. Decoder circuitry for decoding the syndrome bits and effecting the control signals for controlling the correction of single bit errors is described. The syndrome bits are applied to the adder circuits in predetermined groupings, and the carry signals from each of the adder circuits are applied to circuitry for detecting the occurrence of multiple bit errors. Selected ones of the decoded syndrome bits are utilized to determine the occurrence of single bit errors.