Fast error checked multibit multiplier

Abstract

A high speed multiplier circuit is disclosed which not only provides increased performance for the multiply operations of a large scale processor but also provides for single bit error detection of results as well. It incorporates a gated carry/save adder array to eliminate the decoding of multiplier characters thereby reducing logic levels and enhancing performance. A means is illustrated for detecting single bit errors without redundancy or performance loss. While the array proper is more complex than other multibit algorithms, the multiplexers needed by those earlier systems are no longer required. The small increase in complexity of the array proper eliminates the need for decoding of the multiplier bits or other interaction between the multiplier groups. The net effect is a reduction in logic with faster operation because of the omission of the decoding requirement.