Phase comparator using two capacitors alternately charged via constant

Abstract

One of two capacitors in a phase comparator is discharged for a logic zero data input and is alternately charged with opposite polarities, depending on the state of a regenerated clock signal, for a logic one data input. The resultant charge of the capacitor when the data input again becomes zero is used to control a variable frequency oscillator which produces the clock signal, while the other of the two capacitors is discharged and then charged in the same manner. A phase locked loop including the phase comparator can accommodate arbitrary data sequences of a return-to-zero data signal and does not require a low pass filter.