Multiplier/adder circuit

Abstract

In one embodiment of this invention, a uniquely designed switched capacitor multiplier/adder (129) is provided which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit significantly reduces the space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This invention provides a novel structure and method which minimizes error components in the synthesized speech signal due to voltage errors inherent in the use of analog sample and hold circuits which are used to store the forward and backward prediction errors utilized in the linear predictive coding technique. Using the method of this invention, the inherent error components are alternatively inverted and not inverted upon each clock cycle of the multiplier/adder. Thus imposing a frequency of one-half the clock rate upon the error components. These error components are then removed using a notch filter which removes signals having a frequency of one-half the clock rate.