The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 1985
Filed:
Sep. 16, 1982
Applicant:
Inventor:
Chitranjan N Reddy, Houston, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307482 ; 307443 ; 307481 ; 307578 ; 307269 ;
Abstract
A clock circuit for producing a high-level delayed clock output following an input clock employs an output transistor and pull-down transistor controlling an output node in response to the voltage on a drive node. The input clock is applied to this drive node by a decoupling arrangement, consisting of two series transistors. The first transistor isolates the input charge on a holding node, and the second of the series transistors transfers the charge to the drive node after the desired delay. The output node is held at zero until after the delay, with no unwanted voltage rise, and no d.c. power loss. A large capacitive load can be driven.