The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 1985
Filed:
May. 22, 1981
Ronald H Gruner, Cary, NC (US);
Gerald F Clancy, Saratoga, CA (US);
Craig J Mundie, Cary, NC (US);
Steven J Wallach, Saratoga, CA (US);
Stephen I Schleimer, Chapel Hill, NC (US);
Walter A Wallach, Jr, Raleigh, NC (US);
John K Ahlstrom, Mountain View, CA (US);
David H Bernstein, Ashland, MA (US);
Michael S Richmond, Pittsboro, NC (US);
David A Farber, Durham, NC (US);
John F Pilat, Raleigh, NC (US);
Richard A Belgard, Saratoga, CA (US);
Richard G Bratt, Wayland, MA (US);
Data General Corporation, Westboro, MA (US);
Abstract
A digital computer system including a memory and a processor. The memory operates in response to memory commands received from the processor. Items of data stored in the memory include instructions to which the processor responds. Each instruction contains an operation code which belongs to one of several sets of operation codes. The meaning of a given operation code is determined by the operation code set to which the instruction belongs. Some of the instructions also contain names representing items of data used in the operation specified by the operation code. The processor includes an operation code decoding system which decodes the operation code as required for the instruction set to which it belongs, a name resolution system for deriving the address of the data item represented by a name from the name using an architectural base address contained in the name resolution system, and a control system which controls the operation of the processor. The processor performs a call operation and a return operation. Only the call operation and the return operation may change the current architectural base address. The memory further contains name table entries associated with the names. Each name table entry contains information used by the name resolution system when it resolves a name.