The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 1985
Filed:
Jun. 15, 1983
Jack A Schroeder, Scottsdale, AZ (US);
Ernel R Winkler, Mesa, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
An improved VLSI device package and an improved method for contacting VLSI devices, in which the occurrences of wire bond shorts and lead voltage drops are substantially reduced, are obtained by providing multiple lead levels in the package, with the N.sub.2 leads on the upper lead level grouped into N.sub.3 bunches separated by N.sub.4 spaces, where each of the N.sub.4 spaces aligns with a bonding target on a corresponding one of the N.sub.1 leads on the lower level leads of the package, and where N.sub.1 <N.sub.2, preferably N.sub.1 .ltoreq.20 to 30% of N.sub.1 +N.sub.2. Wire bonds from the device to the N.sub.1 lower level leads align with the bonding targets, so that wire bonds from the device to the N.sub.2 upper level leads lie in clear corridors between the bonds to the N.sub.1 lower level leads. In this way wire bond crossovers and shorts are avoided. The N.sub.1 lower level leads can be made wide and short and are used for the high current connections. Other leads can also be made wider, thus reducing inductive and resistive voltage drop in the package.