Simultaneous load and verify of a device control store from a support

Abstract

The loading (writing) of plural successive data strings of specifiable bit-length and numbers to a scan/set testable register (called a CONTROL STORE SCAN LOOP STRING) from which it may then be transferred to a control store (called a CONTROL STORE (RAM)) both within a remote slave digital logic device (called a CENTRAL COMPLEX) is bit-serially conducted upon one signal line of a scan/set network by a controlling digital logic device (called a SUPPORT PROCESSOR) in substantially simultaneous time to the reading of the previous contents of such register (and control store) bit-serially via another signal line of said scan/set network. Both signal lines and devices together form a circular BIT-SERIAL SCAN LOOP, upon which the bit-serial writing and reading is time overlapped. The data strings read are the echo-back of the data strings previously written, and are, in a first operational mode called ECHO, lodged in a buffer memory (called a SCAN/SET BUFFER) of the controlling digital logic device wherein, subsequent to communication, they may be programmably compared with the data strings written in verification of process integrity. In a selectable alternative second operational mode called VERIFY, each successive data string read back is, in substantially simultaneous time, automatically compared with the data string as previously written. Thusly, loading (writing) and reading and verifying activities on variably specifiable numbers of data strings of variably specifiable bit-length communicated upon a BIT-SERIAL SCAN LOOP all transpire substantially concurrently in simultaneous time.