High speed buffer allocation apparatus

Abstract

A high speed data buffer array allocation circuit is provided in association with a plurality of buffer memories for directing high speed data into the memories. The circuitry employs high speed MOS technology to implement high speed switching and data allocation. The data packet input, generally from an uninterruptible source, is directed and written into a first available buffer memory. The memory can thereafter be read by a host computer. Flags are set indicating the availability of the memory for reading. The data buffer allocation circuit has a plurality of selection circuits connected in an ordered linear array for effectively passing therethrough to the circuit associated with the first available buffer, a data ready input signal. In response to the data ready input signal, the selection circuit and associated gating circuit provide the necessary control to direct the data to the associated memory and to thereafter leave a flag indicating the availability of data. The selection circuit further latches a pass-through element of the circuit to a conductive state whereby the next data ready input signal is passed to a succeeding buffer along said array. When data is read by, for example, the host computer, the buffer selection circuit returns to an operating state wherein the data ready signal is isolated from succeeding selection circuits and the data available flag is removed.