A/d converter with bit extension capability using wired-or outputs

Abstract

A parallel comparator includes a plurality of comparator portions each having first and second transistors differentially connected. The first transistors have their bases connected to receive an analog input signal, whereas the second transistors have their bases connected to receive reference voltages having different levels. Among the plural comparator portions, the collector of the first transistor and the collector of the second transistor are connected with a load in accordance to a predetermined rule. An A/D converter for converting an analog input signal into digital signals of plural codes is also provided which includes a critical detecting comparator for generating a detection output at a predetermined level when the digital signals of the plural codes are converted into such an analog signal as effects the overflow or underflow. The A/D converter includes a control circuit for forcibly controlling the levels of the digital signals of the plural bits in case the detection output of the critical detecting comparator reaches a predetermined level.