The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 1985
Filed:
Mar. 03, 1982
Vladi Pusic, San Jose, CA (US);
Benjamin T George, Sunnyvale, CA (US);
Monte E Smith, St. Paul, MN (US);
Craig B Johnson, Shoreview, MN (US);
Sperry Corporation, New York, NY (US);
Abstract
A data processing system has a host processor, a RAM, a cache memory for storing segments of data, a plurality of disk drive devices and a storage control unit for controlling data transfers, data from the host processor being written to the cache memory and subsequently destaged to the disks. The storage control unit continuously updates a variable indicating the number of written-to segments resident in the cache memory that have not been destaged to the disks. The variable is stored in the RAM. A File Status flipflop is responsive to the variable to produce a 'good file' signal when the variable is zero. The File Status flipflop is provided with an auxiliary power supply to maintain it in its present state in the event all power to the cache memory is terminated. Upon restoration of power after a complete power loss, the output of the status flipflop may be sampled by a command from the host processor to find out if any data was lost because written-to segments were present in the cache memory at the time all power was lost. The output of the File Status flipflop is also utilized to inhibit manually actuated functions which would destroy or invalidate written-to segments in the cache memory if the power to the cache memory were turned off, the cache memory were taken off line, or the port select switches between cache memory and the storage control unit were actuated to change port connections.