Method of making a planar inp insulated gate field transistor by a

Abstract

A planar compound semiconductor insulated gate field effect transistor and a virtual self-aligned process for making the same. The device includes a semi-insulating InP substrate in which doped source and drain regions separated by a channel region are located. An insulated gate is located on the surface of the substrate over the channel region. The device is fabricated by a virtual or partially self-aligned method wherein the channel region is defined by forming channel alignment insulating layers on the surface of the substrate. Source and drain regions, aligned with the channel alignment layers, are formed in the substrate by ion-implantation. The remainder of the device is formed on the surface of the substrate.