Dynamic reference potential generating circuit arrangement

Abstract

This dynamic reference potential generating circuit arrangement is especially adaptable to a binary data storage array of the type wherein each data storage cell comprises a single transistor and a single capacitor. A reference potential generating circuit for such an array comprises a pair of such identical transistors connected in parallel and a pair of identical capacitors, connected in common to the transistor emitter electrodes which capacitors couple the emitters to a digit line and to a refresh line, respectively. This arrangement develops a potential swing at the emitter electrodes equal to half of the potential swing that would develop at the emitter electrode of the transistor of a single data storage cell for the same signal swing on the digit line. Basically, the total capacitance connected to the emitter electrode of the generator circuit transistors is twice the capacitance connected to the emitter electrode of the transistor of a single storage cell. Therefore, the potential applied through the capacitor to the emitter electrode is exactly half of that applied through the capacitor connected to the storage cell transistor emitter electrode.