The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 1985
Filed:
May. 02, 1983
Howard H Luh, Sunnyvale, CA (US);
Ford Aerospace & Communications Corporation, Detroit, MI (US);
Abstract
A lossless and matched dual mode network (10) in which the maximum voltage amplitudes (a, b, and c, respectively) appearing at three output ports (11, 12, 13), are preselected and are arbitrary subject only to the constraint that the sum of the squares of any two elements of the set (a, b, c) must be equal to or greater than the square of the third element of this set. The set of complex voltages (A, B, and C, respectively) appearing at the three output ports (11, 12, 13) when an input signal is applied to one of the input ports (1 or 2) is conjugate with the set of output voltages (AA, BB, and CC, respectively) appearing at the three output ports (11, 12, 13) when an input signal is applied to the other input port, which is isolated from the initially selected input port (1 or 2). The network (10), which may be used as a feed network in an antenna (25) system, e.g., as an even/odd mode network, comprises three 90.degree. couplers (31, 32, 33 ) and three phase shifters (41, 42, 43). The couplers (31, 32, 33) have preselected characterizing angles (T1, T2, and T3, respectively), which are specified herein. Similarly, the three phase shifters (41, 42, 43) impart preselected phase shifts (P1, P2, and P3, respectively), which are similarly specified herein. In a first embodiment, the first input port (1) is coupled to a first input of the third coupler (33); in a second embodiment, the first input port (1) is coupled to a second input of the third coupler (33).