Power up reset pulse generator

Abstract

A power up reset pulse generator circuit provides a reset pulse to initialize the states of logic elements in a low power field effect transistor (FET) integrated circuit. The reset pulse generator includes a pair of P-channel enhancement FETs and a first capacitor connected in a series charging path between V.sub.DD and V.sub.SS power supply terminals of the integrated circuit. A second capacitor, and a pair of N-channel enhancement FETs are connected in a second series charging path between the V.sub.DD and V.sub.SS terminals. The second capacitor is connected between the V.sub.DD terminal and an output node, at which the reset pulse is provided. Before power is applied, the first and second capacitors are uncharged and all four FETs are off. When power is applied and the potential between V.sub.DD and V.sub.SS terminals exceeds twice the P-channel threshold voltage, the P-channel FETs turn on, thereby allowing the first capacitor to begin charging. In the meantime, the voltage at the output has followed V.sub.DD, since the N-channel FETs remain off. When the voltage across the first capacitor exceeds twice the N-channel threshold voltage, the N-channel FETs turn on, thereby allowing the second capacitor to charge and the potential at the output terminal to move toward the potential of the V.sub.SS terminal. After the initial reset pulse is generated, the first and second capacitors are charged to approximately the potential between the V.sub.DD and V.sub.SS terminals, and the circuit consumes no static power.