Circuit for checking bit errors in a received bch code succession by the

Abstract

For use in deciding whether a single or a t-tuple error (t being greater than unity) is present in each bit sequence given as a primitive BCH code in accordance with a generator polynomial comprising a primitive and a non-primitive polynomial, an error checking circuit comprises first and second dividers (16, 17) for dividing each bit sequence by the primitive and the non-primitive polynomials to provide first and second signals, respectively. If the bit sequence includes only a single error, the first signal represents one of non-zero residues which result by the division when such single errors are present at the respective bit locations of the sequence. A memory (18) is preliminarily loaded with reference numbers corresponding to the respective non-zero residues and produces one of the reference numbers in response to the first signal only in the presence of a single error. A comparator (19) compares the produced reference number with a residue represented by the second signal to carry out the decision. Preferably, the memory is loaded also with the single error bit locations to locate the single error in a bit sequence being checked. The circuit may be a microcomputer operable in the above-described manner.