The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 1985

Filed:

Apr. 12, 1984
Applicant:
Inventor:

Robert J Proebsting, Dallas, TX (US);

Assignee:

Mostek Corporation, Carrollton, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
371 28 ; 324 / ; 365201 ; 371 21 ;
Abstract

A semiconductor memory circuit (140) includes a plurality of memory cells each having an access transistor (154, 158) and a storage capacitor (162, 166). The memory cells are connected to digit lines (142, 144) each of which is split into halves each connected to one input of a sense amplifier (146, 148). The sense amplifiers (146, 148) operate to pull one of the half digit lines connected thereto to ground while a pull up circuit (220) operates to elevate the other half digit line to the supply voltage. A margin test circuit receives through a control pin (236) an externally supplied test command which generates a test signal (318) to generate marginal low and marginal high voltage states to be written into the memory cells. The marginal low voltage state is generated by a voltage divider (288). The marginal high voltage state is generated by disabling the pull up circuit (220). To prevent loss of the marginal low state the sense amplifiers (146, 148 and 248) are disabled by the internally generated test signal. While the externally supplied test command is applied to the semiconductor memory circuit (140) marginal voltage states are applied to memory cells in accordance with externally supplied address and operational commands. The marginal voltage states are utilized to simplify testing of the circuit.


Find Patent Forward Citations

Loading…