Dma bus load varying unit

Abstract

A DMA bus load varying unit applied to a data processing system has a DMA bus and a memory connected to the DMA bus is provided with a mode designating circuit for designating a memory read and write operation, a continuous operation of the memory read and write operation, and a start and stop operation of the memory read and write operation for the memory, a clock-pulse generator connected to said mode-designating circuit, a period counter connected to the clock-pulse generator for counting clock-pulse signals from the clock-pulse generator, a period-setting circuit for specifying an arbitrary period, a first comparator for comparing the output from the period counter with the output from the period-setting circuit and for producing a first coincident signal when they are equal, a flip-flop connected to the first comparator for producing the DMA bus request signal in accordance with the coincident signal; DMA bus circuit connected to the mode-designating circuit and the flip-flop which is triggered by the DMA bus request signal and performs the memory access through the DMA bus in accordance with the mode designated by the mode-designating circuit, a size counter connected to the DMA bus circuit for counting the number of the DMA bus cycles of said DMA bus circuit, a transfer data size-setting section for specifying an arbitrary transfer data size, a second comparator for comparing the output from the size counter and the output from the transfer data size-setting section and for producing a second coincident signal when they are equal, the second coincident signal being supplied to initialize the DMA bus circuit, and a timer for counting clock pulses from the clock pulse generator to perform time measurement until a specified data transfer is completed.