The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 1985

Filed:

Dec. 23, 1981
Applicant:
Inventors:

Kazunari Shirai, Yokohama, JP;

Izumi Tanaka, Yokohama, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 23 ; 357 41 ; 357 45 ; 365185 ;
Abstract

The present invention is an improvement of a semiconductor memory device, preferably a PROM or a mask ROM, wherein: MOS transistors are formed in a semiconductor substrate, are arranged in rows, and are isolated from each other by a plurality of field insulation films arranged in an island pattern; the MOS transistors aligned in one of the rows have one common gate which extends over one row of field insulation films; the MOS transistors aligned in one of the rows have a common first region for forming a drain or a source parallel to the common gates; and a second region for forming another drain or source is surrounded by a pair of common gates and a pair of field insulation films so that a plurality of second regions are isolated from each other. According to the present invention, the field insulation films and the common gates are delineated to coincide with one another at the ends thereof facing the common first region using a mask film extending between a pair of common gates and covering the region between the pair of common gates and the part of the common gates not covered by the mask film.


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