The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 1985
Filed:
Aug. 30, 1982
Moises Cases, Delray Beach, FL (US);
Wayne R Kraft, Coral Springs, FL (US);
William L Stahl, Jr, Coral Springs, FL (US);
Nandor G Thoma, Boca Raton, FL (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed 'modified' PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.